The present invention relates generally to the recordation and reproduction of eight-to-fourteen modulation (EFM) data, and more particularly, to a phase locked loop (PLL) and method for generating an EFM data restoring clock signal.
Variable speed playback systems can be used to play pre-recorded data independent of their spindle motor speed, although such systems ordinarily encounter difficulties in properly reproducing EFM data recorded at a speed set by a fixed clock signal. A restoring clock signal, such as generated by a PLL, is needed to properly reproduce the EFM data.
Conventional PLLs are limited to phase detection in a capture range of +10 to -10 clock pulses. Some types of playback systems which have four or more multiple speeds, such as CD-ROM players or digital video disk players, need PLLs capable of a wider capture range to gain access to EFM data that has been recorded at a higher speed.
As described further with reference to FIG. 1, prior art PLLs suffer from several problems. One form of conventional PLL has a wide capture range that can detect some pre-set maximum number of clock pulses (T.sub.max ) occurring between a rising edge and a falling edge of a reproduced EFM data signal. This type of PLL can measure the detected number of clock pulses against a reference clock cycle to control a generated clock signal frequency. This process, however, is slow and requires a considerable amount of time to vary the generated clock signal frequency.
A variation on this form of conventional PLL varies the clock signal frequency by selecting from among several detected T.sub.max values. This approach is also slow and requires a considerable amount of time to generate a restoring clock signal, thereby leading to delays often comparable to the delay incurred by a disk access operation.
A further problem with conventional PLLs is that they typically require a considerable amount of time to be configured into a locking range.